MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202611024573 A) filed by Dr. Kiran Kumar Paidipati; Hyndhavi Komaragiri; and Dr. Talari Ganesh, Sirmaur, Himachal Pradesh, on March 2, for 'a closed-loop physiological glycemic response prediction and adaptive diet control system with measurable technical effect.'
Inventor(s) include Dr. Kiran Kumar Paidipati; Hyndhavi Komaragiri; and Dr. Talari Ganesh.
The application for the patent was published on May 1, under issue no. 18/2026.
According to the abstract released by the Intellectual Property India: "The present invention relates to a closed-loop glycemic response adaptive dietary control system for diabetes management. The system integrates a continuous glucose monitoring interface, a physiological glucose kinetic modelling engine, a hierarchical hybrid optimization module, and an adaptive recalibration controller executed within an edge-computing framework. Real-time glucose measurements acquired from a glucose sensing device are processed to generate individualized predictive glycemic response parameters including postprandial spike amplitude and glycemic variability indices. The predictive parameters are utilized within a multi-layer optimization architecture comprising medical safety constraints, glycemic response minimization objectives, nutritional sufficiency requirements, and cost-weighted selection criteria. The system continuously compares predicted glucose responses with subsequently acquired physiological measurements and dynamically recalibrates dietary composition upon detection of deviation beyond predefined thresholds. Partial execution of modelling and constraint enforcement functions on an edge device reduces recalibration latency and network dependency. The invention thereby achieves measurable reduction in predicted postprandial glucose spike amplitude and glycemic variability through integration of physiological modelling, hierarchical hybrid optimization, and real-time sensor-driven feedback within a closed-loop computational architecture."
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