MUMBAI, India, Feb. 6 -- Intellectual Property India has published a patent application (202511133282 A) filed by Manipal University, Jaipur, Rajasthan, on Dec. 30, 2025, for 'a fault-tolerant routing system and method for two-dimensional network-on-chip.'
Inventor(s) include Dr. Manoj Kumar Bohra.
The application for the patent was published on Feb. 6, under issue no. 06/2026.
According to the abstract released by the Intellectual Property India: "The present invention relates to a fault-tolerant routing system and method for two-dimensional network-on-chip. The fault-tolerant routing algorithm can tolerate all single-link. The method comprises: maintaining fault information in four directional registers at each router; hereby enabling advance detection and awareness of faults; upon detection of a fault, the register entries of neighboring routers are dynamically updated; and fault-free routing paths are selected from the available paths based on the stored fault status and predefined turn-restriction rules. The invention fixed size register reduces the long table requirement at each router that generally dramatically increases with network size. The heat-map shows that the proposed distributes traffic more evenly in faulty networks and thus achieves significant performance improvement for network throughput. The hardware overhead of the proposed work is also low as it works on a turn model, which eliminates the requirement of a virtual channel and uses fixed smaller register entries."
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