MUMBAI, India, May 30 -- Intellectual Property India has published a patent application (202311079994 A) filed by Professor Sajad A Loan; Hafsa Nigar; and Dr. Mohd Haris, New Delhi, on Nov. 24, 2023, for 'a high performance uni-gate v ertical power mosfet : a method of manufacturing the same.'
Inventor(s) include Professor Sajad A Loan; Hafsa Nigar; and Dr. Mohd Haris.
The application for the patent was published on May 30, under issue no. 22/2025.
According to the abstract released by the Intellectual Property India: "A novel uni-gate vertical power MOSJ'ET structure is proposed and the smethod of fabricating it is given. A single gate is used in the structure located below the source and the channel region. The vertical n-sourcefpbase junction and the lateral p-base/n-drift junction in the structure suppresses the parasitic n-p-n transistor effect, thus providing a better BV- . Ron tradeoff. The use of single gate instead of two buried gates removes the problem of integrate interference thus allowing better scaling of the device. The lower cell pitch thus used in the device reduces its specific ON resistance at the same breakdown voltage, thus providing an increment in the Baliga's figure of merit. Suppressing integrate interference, the single gate also allows a higher drift doping concentration without any significant reduction in its breakdown voltage. The higher drift doping reduces the drift resistance and thus the total ON resistance of the device and switching losses. The cell pitch reduction and the high drift doping together provides the specific ON resistance of 25.3lmohm.mm2 in the proposed device, at a breakdown voltage of 68V, together giving the Baliga's figure of merit of 17.99MW fcm2. The use of single gate also reduces the parasitic gate charge and switching losses."
Disclaimer: Curated by HT Syndication.
