MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641049579 A) filed by Srinivasa Ramanujan Institute Of Technology; Dr. M. L. Ravi Chandra; C. Jahnavi; G Kumar Raja; and B. Kiran Kumar, Ananthapuramu, Andhra Pradesh, on April 18, for 'a multi-layer secure image encryption framework leveraging memristive chaos for efficient protection.'
Inventor(s) include Srinivasa Ramanujan Institute Technology; Dr. M. L. Ravi Chandra; C. Jahnavi; G Kumar Raja; and B. Kiran Kumar.
The application for the patent was published on May 1, under issue no. 18/2026.
According to the abstract released by the Intellectual Property India: "The primary objective of the present invention is to design and develop a secure and hardware-efficient colour image encryption system that overcomes the limitations of conventional RGB image encryption techniques. Secure transmission of colour images over open networks is challenging due to high redundancy and strong inter-pixel correlation inherent in image data, while many existing encryption schemes achieve high security at the cost of increased hardware complexity and power consumption, making them unsuitable for real-time applications. The proposed work presents an optimized triple-layer RGB image encryption scheme based on multiple hyperchaotic systems, wherein the red, green, and blue colour channels are processed and encrypted independently to ensure strong confusion and diffusion properties. In contrast to conventional approaches employing complex 8-to-1 transformation models, the proposed system introduces a modified 4-to-1 transformation architecture while preserving the multi-layer hyperchaotic encryption structure, thereby significantly reducing hardware overhead without compromising encryption strength. The system utilizes memristor-based, seven-dimensional, and laser-based hyperchaotic systems for generating highly random and sensitive key streams with strong statistical properties. The design is implemented using Verilog HDL and synthesized on an FPGA platform using Quartus II, enabling efficient hardware realization. Experimental results demonstrate a considerable reduction in logic utilization and power consumption while maintaining comparable operating speed. Security analysis confirms high entropy, low pixel correlation, and strong resistance against statistical and differential attacks. By effectively integrating robust security mechanisms with an optimized hardware architecture, the proposed system provides a reliable and scalable solution for real-time, low-power image encryption applications in secure communication, surveillance, medical imaging, and defence systems."
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