Intellectual Property India Publishes Patent Application for 'A Non-Stateful Voltage-Mode Logic Architecture Using Resistive Random Access Memory (RRAM) As A Resistive Pull-Up Element' Filed by Srinivasa Ramanujan Institute Of Technology; Mr. D. Sreekanth Reddy; K. Yaswanth Reddy; B. Kavyaroopini; and A. Sudarshan

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641050606 A) filed by Srinivasa Ramanujan Institute Of Technology; Mr. D. Sreekanth Reddy; K. Yaswanth Reddy; B. Kavyaroopini; and A. Sudarshan, Ananthapuramu, Andhra Pradesh, on April 21, for 'a non-stateful voltage-mode logic architecture using resistive random access memory (rram) as a resistive pull-up element.'

Inventor(s) include Srinivasa Ramanujan Institute Technology; Mr. D. Sreekanth Reddy; K. Yaswanth Reddy; B. Kavyaroopini; and A. Sudarshan.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "The present invention proposes a non-stateful voltage-mode logic architecture using Resistive Random Access Memory (RRAM) as a fixed resistive pull-up element in conjunction with an NMOS transistor pull-down network. Unlike conventional CMOS logic that utilizes PMOS transistors and existing memristive logic approaches that rely on resistance switching, the proposed system operates without resistance state transitions during computation. This enables improved device endurance, reduced circuit complexity, and lower transistor count. The architecture supports implementation of fundamental Boolean logic functions and is suitable for low-power digital applications."

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