MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202611050132 A) filed by Graphic Era Hill University, Dehradun, Uttarakhand, on April 20, for 'a system and method for adaptive compiler-assisted parallel graph processing with dynamic race detection and feedback-based optimization on heterogeneous architectures.'
Inventor(s) include Sarthak Pundir; Dr. Arun Pratap Singh Rathod; Sushant Chamoli; Manika Manwal; and Sonali Gupta.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "The present invention relates to compiler-assisted graph processing in heterogeneous environments. A user device receives graph algorithm specifications expressed in a domain-specific language (DSL) which are parsed by a Graph Algorithm Parser (1) to extract vertices, edges, and traversal and synchronization semantics. An Intermediate Representation Generator (2) transforms an abstract syntax tree into a graph-aware intermediate representation annotated with metadata for topology, dependencies, and memory access patterns. An Integrated Compiler Unit (3) performs static analysis and inserts dynamic race detection instrumentation via runtime hooks utilizing shadow memory, while an Architecture-Specific Code Generator (4) produces optimized executable binaries for multi-core CPUs and GPUs. Additionally, non-volatile memory storage archives performance logs and representations, with a Performance Analysis and Optimization Unit (5) iteratively adjusting execution parameters based on runtime metrics."
Disclaimer: Curated by HT Syndication.
