MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202611049088 A) filed by Arvind Kumar Singh, Sonbhadra, Uttar Pradesh, on April 17, for 'adaptive reasoning engine: hardware-optimized methods for sparse expert routing, adaptive compute halting, persistent memory management and difficulty-caliberated training.'

Inventor(s) include Arvind Kumar Singh.

The application for the patent was published on May 29, under issue no. 22/2026.

According to the abstract released by the Intellectual Property India: "The present invention discloses five hardware-anchored methods and systems, protected by eight claims, for optimizing the parallel execution efficiency, VRAM bandwidth utilization, and compute cycle allocation of hardware-accelerated neural networks combining sparse expert routing with adaptive computation. (1) Hardware Utilization Feedback Signal (Claims 1, 6): L_CV = Var(load)/Mean(load)^2 - dimensionless, scale-invariant, fully-differentiable, mitigates bandwidth saturation across 8 to 10,000 expert units without hardware-specific re-calibration. (2) Expert-Consensus Compute-Cycle Gating / EOCAH (Claim 2): hardware feedback circuit conditioning compute-cycle gating on routing-weighted expert outputs, physically releasing tensor core resources upon expert consensus. (3) Backpropagation Buffer Overflow Prevention / EDMP (Claims 3, 7): differentiable read controller + gradient-isolated write controller with 0.95/0.05 EMA updates, maintaining O(1) constant memory footprint across unbounded sequential cycles. (4) VRAM Bandwidth-Efficient Gate-Broadcast GPU Kernel / 2D-GBK (Claim 4): Triton kernel achieving n_slots-fold reduction in VRAM bandwidth via 2D gate-broadcast amortization, 3.1x measured throughput improvement. (5) Asymmetric Hardware Resource Allocation / DODCT (Claims 5, 8): large oracle ( = 7B params) in isolated VRAM partition via REST API + small oracle ( 150M params, = 47:1 ratio) in on-device stream for per-token entropy scoring at 100x+ throughput to directly supervise compute-cycle gating without data-bus stalling."

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