MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541122801 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on Dec. 5, 2025, for 'approximate unsigned multiplier with compressor-based partial product reduction.'
Inventor(s) include Dr. Aarthy M; and Ms. Kowshalya R.
The application for the patent was published on Jan. 2, under issue no. 01/2026.
According to the abstract released by the Intellectual Property India: "The present disclosure provides an approximate unsigned multiplier system (300) that includes an input processing unit (302) configured to receive a first binary operand and a second binary operand, a partial product generation stage (308) coupled to the input processing unit (302) and configured to generate partial products through bitwise multiplication of the first binary operand and the second binary operand using an AND gate array (310), an approximate reduction stage (314) coupled to the partial product generation stage (308) and configured to process the partial products using different approximation strategies based on bit significance levels where higher-order bit positions are processed using higher precision techniques and lower-significance bit positions are processed using greater approximation techniques, and a final addition stage (322) coupled to the approximate reduction stage (314) and configured to combine the processed partial products into a final multiplication result."
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