MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641048371 A) filed by Seshadri Rao Gudlavalleru Engineering College; Mrs. T. Venkata Lakshmi; Chebrolu Sriharsha; and Devanaboyina Anusha, Gudlavalleru, Andhra Pradesh, on April 16, for 'design of low-power 8-bit multiplier using approximate adders for error tolerant applications.'
Inventor(s) include Seshadri Rao Gudlavalleru Engineering College; Mrs. T. Venkata Lakshmi; Chebrolu Sriharsha; and Devanaboyina Anusha.
The application for the patent was published on May 1, under issue no. 18/2026.
According to the abstract released by the Intellectual Property India: "Binary multiplication is a key arithmetic operation in digital systems, but conventional exact multipliers consume considerable power and area because of the large number of adder cells used in the partial product accumulation stage. The present disclosure proposes a low power 8-bit multiplier architecture in which already existing approximate adder logics, referred to as Approximate Adder 1 and Approximate Adder 2, are selectively incorporated into the less significant positions of a carry-save reduction tree, while exact adders are preserved in more significant positions. The novelty of the disclosure lies in the proposed multiplier architecture and the selective deployment of known approximate adder circuits within that architecture, and not in the design of any new approximate adder logic. By integrating known approximate adders in selected non-critical locations, the architecture aims to reduce power consumption and hardware complexity while maintaining acceptable computational accuracy for error-tolerant applications such as DSP, image processing, and embedded systems. Keywords: Approximate Computing, Low-Power Multiplier, Carry-Save Multiplier, Approximate Adder, Partial Product Accumulation, Image Processing, VLSI, DSP."
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