MUMBAI, India, June 6 -- Intellectual Property India has published a patent application (202517017255 A) filed by Google Llc, Mountain View, U.S.A., on Feb. 27, for 'efficient multiple garbled circuit protocol.'
Inventor(s) include Wang, Gang; and Yung, Marcel M. Moti.
The application for the patent was published on June 6, under issue no. 23/2025.
According to the abstract released by the Intellectual Property India: "This document describes systems and techniques for using cryptography, secure MPC, garbled circuits, and oblivious transfer to select digital components in ways that preserve user privacy and protects the data of each party involved in the selection process. In one aspect, a method includes receiving, from a content platform by a first computer of a secure MPC system, a first garbled circuit for determining whether each of a first set of digital components satisfies a publication condition for display with a resource. The first computer evaluates the garbled circuit to obtain, for each digital component in the first set of digital components, a first secret share of a publication condition parameter that indicates whether the digital component satisfies the publication condition. The first computer generates a second garbled circuit for determining whether each digital component in a second set of digital components is eligible for display with the resource."
The patent application was internationally filed on July 19, 2024, under International application No.PCT/US2024/038679.
Disclaimer: Curated by HT Syndication.
