MUMBAI, India, Nov. 14 -- Intellectual Property India has published a patent application (202547098530 A) filed by Qualcomm Incorporated, San Diego, on Oct. 13, for 'field-effect transistors (fets) employing thermal expansion of work function metal layers for strain effect and related fabrication methods.'
Inventor(s) include Li, Xia; Yang, Bin; and Yuan, Jun.
The application for the patent was published on Nov. 14, under issue no. 46/2025.
According to the abstract released by the Intellectual Property India: "Forces applied to the channel regions of semiconductor slabs in a first direction relative to the semiconductor slab, can create strains in the crystal structure that improve carrier mobility to improve drive strength in the channel region. In a three-dimensional (3D) FET structure (600), a work function metal layer (616) is provided on opposing faces of semiconductor slabs, for example nanosheets, to cause a force to be exerted on the channel regions (604(1), (2), (3)) in a first direction corresponding to current flow. A gate dielectric (612) is present between the channels (604(1), (2), (3)) and the work function metal layer, and furthermore a gate metal (608) surrounds the channels, the gate dielectric and the work function metals. The force in the first direction is either tensile force or compressive force, depending on a FET type (N or P) employing the semiconductor slab, and is provided to create strain in a crystalline structure of the semiconductor slab to improve carrier mobility in the channel region. Increasing carrier mobility in the channel regions in a 3D FET structure increases drive strength of the 3D FET, which saves area in an integrated circuit."
The patent application was internationally filed on May 29, 2024, under International application No.PCT/US2024/031342.
Disclaimer: Curated by HT Syndication.
