MUMBAI, India, Jan. 23 -- Intellectual Property India has published a patent application (202511124962 A) filed by GLA University, Mathura, Uttar Pradesh, on Dec. 11, 2025, for 'finfet-based eleven-transistor static memory bit-cell structure.'
Inventor(s) include Vinay Tomar; Ashish Sachdeva; Divyansh Yadav; and Atharv Sharma.
The application for the patent was published on Jan. 23, under issue no. 04/2026.
According to the abstract released by the Intellectual Property India: "The present invention relates to a FinFET-based static memory bit-cell structure for low-power and high-performance static random-access memory. The bit-cell comprises cross-coupled inverters whose pull-down paths are series-gated by NMOS FinFET transistors to suppress leakage in hold mode, a transmission gate between a write bit-line and a first internal node, a Schmitt-trigger NMOS FinFET in a PN2-style path associated with a second internal node, and a one-sided read stack connecting a read bit-line to a virtual ground node. A single word-line signal simultaneously controls the transmission gate and the Schmitt-trigger device, dynamically shaping internal resistance during write operations, while the decoupled read stack isolates storage nodes from the read bit-line. The structure improves leakage, read static noise margin and write robustness within standard FinFET process flows."
Disclaimer: Curated by HT Syndication.
