MUMBAI, India, Nov. 7 -- Intellectual Property India has published a patent application (202547096552 A) filed by Intel Corporation, Santa Clara, U.S.A., on Oct. 7, for 'floating-point multiply-accumulate unit facilitating variable data precisions.'
Inventor(s) include Anders, Mark A.; Raha, Arnab; Agarwal, Amit; Hsu, Steven; Mathaikutty, Deepak Abraham; Krishnamurthy, Ram K.; and Power, Martin.
The application for the patent was published on Nov. 7, under issue no. 45/2025.
According to the abstract released by the Intellectual Property India: "A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent."
The patent application was internationally filed on Dec. 12, 2023, under International application No.PCT/US2023/083558.
Disclaimer: Curated by HT Syndication.
