Intellectual Property India Publishes Patent Application for 'Fpga-Based Real-Time Haar Wavelet Transform For Image Processing' Filed by Srinivasa Ramanujan Institute Of Technology; Mr. Y. Rajakullayi Reddy; S. Aparna; S. Pavani; and K. Pavithra

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641050592 A) filed by Srinivasa Ramanujan Institute Of Technology; Mr. Y. Rajakullayi Reddy; S. Aparna; S. Pavani; and K. Pavithra, Ananthapuramu, Andhra Pradesh, on April 21, for 'fpga-based real-time haar wavelet transform for image processing.'

Inventor(s) include Srinivasa Ramanujan Institute Technology; Mr. Y. Rajakullayi Reddy; S. Aparna; S. Pavani; and K. Pavithra.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "The Haar Wavelet Transform (HWT) is widely used in image processing applications due to its simplicity, low computational complexity, and efficient multi-resolution analysis capability. This paper presents the design and implementation of a real-time Haar Wavelet Transform using Field Programmable Gate Array (FPGA) technology to achieve high-speed and parallel image processing performance. The proposed architecture exploits the inherent parallelism and pipelining features of FPGA hardware to perform fast decomposition of image data into approximation and detail coefficients. The system is designed to optimize area utilization, memory usage, and processing latency while maintaining high throughput. A streaming-based architecture is adopted to enable continuous real-time image processing without significant buffering delays. The implementation supports multi-level wavelet decomposition, making it suitable for applications such as image compression, denoising, feature extraction, and edge detection.Experimental results demonstrate that the FPGA-based Haar Wavelet Transform significantly improves processing speed compared to software-based implementations while consuming limited hardware resources. The proposed design achieves efficient real-time performance, reduced power consumption, and scalability for high-resolution image processing applications, making it suitable for embedded vision systems and real-time digital signal processing environments."

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