MUMBAI, India, March 13 -- Intellectual Property India has published a patent application (202641024392 A) filed by Erasmus Training Services Private Limited, Hyderabad, Telangana, on March 1, for '"hardware-integrated microarchitectural controller for isa-native negotiation and instruction dispatch".'
Inventor(s) include Sosin Thayyaba Revella; Tarani Talluri; Madhavi Kurapati; Kakumanu Kailaash Sumanth; and Madhu Babu Pallagani.
The application for the patent was published on March 13, under issue no. 11/2026.
According to the abstract released by the Intellectual Property India: "[073] A hardware integrated microarchitectural controller (106, 412) and method for ISA native negotiation and instruction dispatch are disclosed. The system provides a proactive control plane between high level autonomous agents (102) and specialized silicon extensions (116), operating outside neural network weights. A hardware attested Capability Discovery Module (114) probes physical Control and Status Registers (512) to generate an ISA Capability Vector (202) representing verified extensions and power performance envelopes. An Intent Profiling Metadata Engine (108) assigns multi dimensional Instruction Density Metadata (IDM) (204, 414) to agent tasks, capturing characteristics such as vectorizable ratio, branch complexity, sparsity, and related factors. A Negotiation Broker (106, 412), implemented as a microarchitectural state machine, evaluates these signatures against the capability manifest (416), computes an energy efficiency utility score, and issues Physical Control Signals to dispatch tasks to an optimal specialized silicon unit (418, 514) or a Scalar Fallback Core (419, 516, 608). A closed loop feedback mechanism allows specialized units (604) to raise hardware level traps or interrupts (606) on profile mismatch, enabling autonomous re routing and improved throughput per joule in heterogeneous environments."
Disclaimer: Curated by HT Syndication.
