MUMBAI, India, July 11 -- Intellectual Property India has published a patent application (202541060637 A) filed by Dudekula Usen; Mr. B. Mahendra; and Rajeev Gandhi Memorial College Of Engineering And Technology, Nandyal, Andhra Pradesh, on June 25, for 'high speed clock keeper domino logic circuit design using finfet.'
Inventor(s) include Mr. B. Mahendra; Dr. A. Sathish; and Dr. Dudekula Usen.
The application for the patent was published on July 11, under issue no. 28/2025.
According to the abstract released by the Intellectual Property India: "The method of deep sub-micron possesses presented numerous obstacles for the production of semiconductor circuits using CMOS technology, mostly pertaining to power use and propagation latency. In order to create CMOS logic gates, the low leakage clock keeper domino logic (LLCKDL) is a novel technique used in this work is presented. Its goal is to method aims to enhance the gates' noise- decrease in efficiency while reducing the power consumption through leakage. Using an 8 MHz clock frequency, the one FINFET 18 Cadence's nm CMOS technology node can be used to model and build OR gates with 16-bit inputs using the suggested along with current methods. The mean strength consumption of the recommended domino has become better to +5%, better to pervious existing methods. the power delay product(PDP) has been enhanced to +5%, to pervious existing methods."
Disclaimer: Curated by HT Syndication.
