MUMBAI, India, Nov. 7 -- Intellectual Property India has published a patent application (202547096550 A) filed by Qualcomm Incorporated, San Diego, on Oct. 7, for 'reduced training for main band chip module interconnection clock lines.'
Inventor(s) include Godavarthi Lekhya Pavani; Doddi Ravindranath; Ramireddy Harinatha Reddy; Haider Afreen; and V Umamaheshwaran.
The application for the patent was published on Nov. 7, under issue no. 45/2025.
According to the abstract released by the Intellectual Property India: "Aspects relate to reduced training for main band chip module interconnection clock lines. In one example a method includes sending iterations of a first training pattern from a module of a first die to a module partner of a second die on a first main band clock line of a die-to-die connection, the die-to-die connection including a sideband, a main band comprising the first main band clock line, and at least one data line supported by at least the first main band clock line. An automatic result is received from the module partner through the sideband prior to completion of the iterations of the first training pattern, the automatic result indicating successfully receiving the training pattern. Data is communicated with the module partner through the main band using at least the first main band clock line in response to receiving the automatic result."
The patent application was internationally filed on Apr. 10, 2024, under International application No.PCT/US2024/023800.
Disclaimer: Curated by HT Syndication.
