MUMBAI, India, May 30 -- Intellectual Property India has published a patent application (202517043403 A) filed by International Business Machines Corporation, Armonk, U.S.A., on May 5, for 'stacked-fet sram cell with bottom pfet.'
Inventor(s) include Tsutsui, Gen; Mochizuki, Shogo; and Xie, Ruilong.
The application for the patent was published on May 30, under issue no. 22/2025.
According to the abstract released by the Intellectual Property India: "A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source/drain (S/D) epi regions, a top FET including a plurality of top S/D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S/D epi region of the plurality of bottom S/D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN)."
The patent application was internationally filed on June 29, 2023, under International application No.PCT/CN2023/104040.
Disclaimer: Curated by HT Syndication.
