MUMBAI, India, June 26 -- Intellectual Property India has published a patent application (202641071302 A) filed by Vellore Institute Of Technology on June 08, 2026, for A Deterministic Fpga-Based Vehicular Accident Detection And Data Recording System.
Inventors include Konguvel Elango; and Avandhica S R.
The application for the patent was published on June 19, 2026, under issue no. 25/2026.
Abstract: A Deterministic FPGA-Based Vehicular Accident Detection and Data Recording System The present disclosure relates to a deterministic FPGA-based vehicular accident detection and data recording system for real-time crash monitoring and event preservation. The system acquires vehicular operating parameters from an accelerometer sensor, GPS module, brake status input, seatbelt status input, and crash trigger input through parallel hardware interfaces. A hardware-based processing architecture implemented on an FPGA performs crash detection, severity classification, structured event frame generation, and memory control without dependence on operating systems or general-purpose processors. Crash severity is determined using weighted evaluation of acceleration magnitude, crash duration, and change in velocity. The system further employs a dual-phase memory buffering architecture including a pre-crash circular buffer and a post-crash linear buffer for preserving critical vehicular event data before and after crash occurrence. The generated event frames are exported for further analysis and accident reconstruction with deterministic real-time operation.
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