MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202611072004 A) filed by Graphic Era Deemed To Be University on June 10, 2026, for A Device For An Ingaas-Soi Finfet With Reduced Interfacial Defect Sensitivity.
Inventors include Ajay Kumar; Priyanka Agrwal; Neha Gupta; Aditya Jain; and Kaushal Kumar.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: ABSTRACT A DEVICE FOR AN InGaAs-SOI FinFET WITH REDUCED INTERFACIAL DEFECT SENSITIVITY The invention relates to semiconductor devices, and particularly to an InGaAs-SOI tri-gate FinFET architecture having reduced sensitivity to interfacial defects. The device comprises a fin-shaped channel body of In0.53Ga0.47As extending between a source region and a drain region on a silicon-on-insulator support structure with a buried oxide layer beneath the carrier transport path. A HfO2 gate dielectric layer is conformally disposed on three exposed sides of the fin-shaped channel body and a gate electrode is arranged thereover in a tri-gate configuration to define an electric field modulation region and a short-channel control region. The interface region between the fin-shaped channel body and the gate dielectric layer is configured to include donor-like interface trap charges, acceptor-like interface trap charges, or both. The architecture supports enhanced electrostatic control, improved short-channel behaviour, and extraction of transconductance-based linearity metrics under trap-affected operating conditions.
Disclaimer: Curated by HT Syndication.
