MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202611056763 A) filed by Gagan; Akansha Aggarwal; Devender Kumar Soni; Himanshu Marothya; and Vishwas Acharya on May 05, 2026, for A Gate-All-Around Charge Plasma Complementary Fet (gaa-Cp-Cfet).
Inventors include Gagan; Akansha Aggarwal; Devender Kumar Soni; Himanshu Marothya; and Vishwas Acharya.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: The present invention relates to a Gate-All-Around Charge Plasma Complementary Field Effect Transistor (GAA-CP-CFET) and its method of fabrication. The device comprises vertically stacked NMOS and PMOS transistors integrated monolithically through a common gate-all-around structure controlling multiple nanosheet channels for one CMOS pair. Source and drain regions are formed through electrostatically induced charge plasma using work-function-engineered metals, eliminating conventional doping processes. The design employs a shared undoped silicon nanosheet channel to enhance drivability, reduce impurity scattering, and improve threshold stability. Owing to its geometric symmetry, the device allows source/drain interchangeability and concurrent complementary operation under switched gate bias. The proposed structure achieves reduced footprint, minimized interconnect losses, and simplified backend design, offering a compact and energy-efficient solution compatible with advanced technology nodes.
Disclaimer: Curated by HT Syndication.
