MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202611063572 A) filed by Noida Institute Of Engineering & Technology on May 20, 2026, for A High-Speed Error Correction Architecture For Data Transmission.
Inventors include Dr. Sarabjeet Kaur; and Dr. Prachi Tripathi.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: A high-speed error correction architecture for data transmission is disclosed. The architecture includes an input framing interface, a segment distributor, a parallel syndrome computation engine, an adaptive error pattern classifier, a correction mask generator, a pipelined data alignment buffer, a reliability evaluator, a configuration and monitoring unit, and an output delivery interface. Encoded data is segmented, syndrome information is computed in parallel, correction depth is selected adaptively, and aligned payload data is repaired using a generated correction mask. Corrected data is delivered with confidence status.
Disclaimer: Curated by HT Syndication.
