MUMBAI, India, June 22 -- Intellectual Property India has published a patent application (202631043226 A) filed by Indian Institute Of Technology Bhubaneswar on April 04, 2026, for A Low-Noise Dynamic Comparator Featuring A Power-Off Technique.
Inventors include Vijay Shankar Pasupureddi; Subrahmanyam Boyapati; and Maram Srinivasa Rao.
The application for the patent was published on June 12, 2026, under issue no. 24/2026.
Abstract: ABSTRACT TITLE: A Low-Noise Dynamic Comparator Featuring a Power-off Technique The present invention provides a double-tail strongarm latch dynamic comparator system for analog and mixed signal integrated circuits. The present comparator system is suitable for designing energy efficient analog-to-digital converters for IoT applications. The proposed comparator system can be implemented by deploying a cross-coupled load to differential input pair leading to higher preamplifier gain and by using an additional PMOS transistor to switch off power supply after the latch has been regenerated as well as an additional NMOS transistors along with the tail transistor to stop discharge of the preamplifier output nodes below the threshold voltage. The additional PMOS transistors are driven by outputs of the latch stage and the NMOS transistors are driven by the preamplifier output nodes. The present inventions can be used in the design of low power analog-to-digital converters required for wireless sensor nodes or IoT devices. Fig. 1
Disclaimer: Curated by HT Syndication.
