MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202631078725 A) filed by Smunna on June 25, 2026, for A Self-Contained Neuromorphic Binary Computing System Architecture Structurally Map-Defined To Biological Neural Topologies Exclusively Via Text-Deterministic Logic And Register Footprints Without Diagrammatic Dependency.
Inventor includes Rupangshu Manna.
The application for the patent was published on July 17, 2026, under issue no. 29/2026.
Abstract: A HARDWARE-EFFICIENT EDGE COMPUTING ARCHITECTURE FOR NON-SIMULATED BIOLOGICAL-TO-DIGITAL BRAIN REPLICATION AND ARTIFICIAL GENERAL INTELLIGENCE The present invention discloses a highly hardware- efficient digital computing architecture for executing localized, self-contained Artificial General Intelligence (AGI) routines on low- power edge substrates. The architecture establishes a decentralized network matrix composed of dense binary digital microcircuit nodes, wherein each individual microcircuit node physically maps the structural parameters and interconnection paths of a complete four-neuron cortical cluster cleanly within a rigid, deterministic memory footprint of 2 bytes (16 bits). Traditional, power-hungry Floating-Point Units (FPUs) and multi-byte weight matrices are entirely omitted from the design. Instead, the architecture utilizes high-speed 2-bit magnitude hardware comparators to count and evaluate multi-input convergent dendritic paths via direct combinational bit-matching logic. Continuous synaptic leaky paths are simplified into a discrete gating architecture comprising a 1-bit active firing permission switch and a 2-bit dynamic threshold register per neuron. Localized, autonomous hardware learning is driven by an event-driven Dual-Phase Retention Flushing engine that increments or decrements the 2-bit neuron threshold registers based on input signal footprints. To prevent feedback data erasure caused by downstream race conditions, a dedicated Input B Footprint Cache Register Bit is integrated into the 16-bit register map to lock and protect historical feedback states. The address less, bit-mapped structural layout allows multiple microcircuit nodes to be loaded and processed simultaneously within the native CPU registers of legacy 32-bit hardware devices. This design enables massive cognitive processing chains to expand and cascade across localized physical memory channels without software-coded array boundaries, high thermal dissipation, or remote cloud connectivity.
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