MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202621024721 A) filed by Indian Institute Of Technology Indore on March 02, 2026, for A System And Method For Dsp Hardware Ip Security Via Multi-Modal Encoded Transformation And Key-Driven Digest Embedding.
Inventor includes Anirban Sengupta.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: ABSTRACT A SYSTEM AND METHOD FOR DSP HARDWARE IP SECURITY VIA MULTI-MODAL ENCODED TRANSFORMATION AND KEY-DRIVEN DIGEST EMBEDDING The invention relates to the field of digital signal processing intellectual property security and discloses a system comprising an input and pre-processing module for extracting a control data flow graph (CDFG), a scheduled data flow graph generator for creating SDFGs based on vendor-specified resource constraints, and an encoding engine for applying vendor-selected rules to generate encoded bitstreams (B1, B2, B3). A concatenation module merges these bitstreams into a composite m-bit value, which is transformed via circular rotation by a predetermined key d and a modulo operation using an input key x to yield a fixed 128-bit value. A key-driven cipher network splits and encrypts this value through successive rounds with dynamically generated 48-bit keys, followed by a secure hashing module applying SHA-512 to produce a 512-bit digest. Finally, a digital watermark signature is generated via a bit-wise XOR with a vendor-selected key y and embedded in a DSP design register allocation table.
Disclaimer: Curated by HT Syndication.
