MUMBAI, India, Oct. 26 -- Intellectual Property India has published a patent application (202641122603 A) filed by Ms. R. T. Charulatha; Dr. Kiruthiga Devi M; Dr. Golda Dilip; Dr. S. Niveditha; Ms. M. Indumathy; and Dr. V. Rajasekar on October 13, 2026, for Adaptive Digital Vlsi Accelerator For Deep Learning Based Ecg Classification.
Inventors include Ms. R. T. Charulatha; Dr. Kiruthiga Devi M; Dr. Golda Dilip; Dr. S. Niveditha; Ms. M. Indumathy; and Dr. V. Rajasekar.
The application for the patent was published on October 23, 2026, under issue no. 43/2026.
Abstract: ABSTRACT Adaptive Digital VLSI Accelerator for Deep Learning Based ECG Classification The present invention relates to an adaptive digital Very-Large-Scale Integration (VLSI) accelerator for deep learning-based electrocardiogram (ECG) classification. The accelerator comprises an ECG input interface, a preprocessing unit, an R-peak segmentation unit, a reconfigurable one-dimensional convolutional neural network, a parallel multiply-accumulate array, weight and feature memories, and a class-score unit. A signal-quality and confidence controller dynamically selects fixed-point arithmetic precision and the number of active computational lanes according to ECG signal quality, predicted heartbeat class, and classification confidence. The accelerator supports multiple operating modes, including 8-bit fixed-point arithmetic with four active multiply-accumulate lanes, 12-bit fixed-point arithmetic with eight active lanes, and 16-bit fixed-point arithmetic with sixteen active lanes. The controller enables confidence-based recomputation of uncertain heartbeat segments at higher precision. A clock and power controller selectively disables inactive computational lanes and memory banks to reduce unnecessary switching activity. The class-score unit generates heartbeat classifications corresponding to normal, supraventricular, ventricular, fusion, and indeterminate or paced categories, together with associated confidence information. Experimental evaluation on 49,691 held- out heartbeat segments demonstrated an accuracy of 0.6947 for the 12-bit fixed-point model compared with 0.6948 for the 32-bit floating-point model. The estimated weight-memory requirement decreased from 174.77 KB to 65.54 KB, representing a reduction of 62.5%. The accelerator further comprises an event-packet generator that communicates heartbeat classification, confidence, selected operating mode, and alert information for remote monitoring, with waveform data selectively attached when required. The architecture is applicable to wearable ECG monitors, portable cardiac recorders, and remote cardiac-monitoring systems.
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