MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202611043901 A) filed by Indian Institute Of Technology, Jammu on April 06, 2026, for An Apparatus For Accelerating Reductionist Matrix Operations With Guaranteed Linear Memory Traffic.
Inventors include Singh, Dashpreet; Meena, Anil; and Ranjan, Uma Satya.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: Embodiments of the present disclosure relate to an apparatus (100) for accelerating matrix multiplication operations resulting in data of reduced dimensionality. The apparatus (100) includes a hardware-based stream fetcher (102) that retrieves input tensors from an off-chip memory (104) into on-chip buffers while overlapping data transfer with computation. A Streaming Tile-Autonomous Residency (STAR) engine (106) integrates dot-product scoring, online softmax normalization, and probability-value multiplication within a continuous hardware pathway. Intermediate similarity scores and normalization matrices maintain hardware-guaranteed residency on-chip, thereby eliminating repeated write-back cycles to the off-chip memory (104). Such integration transforms attention processing into a compute-centric workflow and reduces memory bandwidth pressure. The hardware-based stream fetcher (102) coordinates data movement with arithmetic stages to sustain throughput across long sequences. By enforcing linear off-chip communication complexity O(N) by restricting external traffic to initial inputs and final results, the apparatus (100) achieves scalable performance, lower latency, and improved energy efficiency.
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