MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202641084683 A) filed by Sivesh Kumar S; R Madhumttha; and Latha P on July 10, 2026, for Asic Implementation Of An Adptive Precision 32-Bit Arithmetic Logic Unit Using Cadence Digital Design Flow.
Inventors include Sivesh Kumar S; R Madhumttha; and Latha P.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: The invention relates to the design and performance evaluation of an Adaptive Precision 32-bit Arithmetic Logic Unit implemented using Verilog HDL and Cadence Digital Design Flow. Unlike conventional fixed-precision ALUs that activate the entire 32-bit datapath for every operation, the proposed architecture dynamically detects the effective operand width and selectively enables 8-bit, 16-bit, or 32-bit computational slices. This adaptive operation significantly reduces switching activity, dynamic power consumption, heat generation, and carry propagation delay while preserving complete computational functionality. The architecture consists of a Precision Detection Unit, Arithmetic Unit, Logic Unit, Shifter Unit, Adaptive Multiplexer, and Flag Generation Unit. The design is synthesized, analyzed, and evaluated using Cadence Digital tools, providing comparisons in terms of area, power, timing. and energy efficiency. The proposed Adaptive Precision ALU is particularly suitable for modem low-power processors, embedded systems, Internet of Things (loT) devices. Digital Signal Processors (DSPs), and Artificial Intelligence edge computing platforms requiring energy-efficient high-performance arithmetic processing.chitecture
Disclaimer: Curated by HT Syndication.
