MUMBAI, India, Oct. 12 -- Intellectual Property India has published a patent application (202621101490 A) filed by National Institute Of Technology Goa on August 21, 2026, for Compact High-Speed Exact Floating Point 16-Bit Multiplier.
Inventors include Perika Puneeth; Amol D Rahulkar; Gaje Sahruday; T. Veerakumar; and Lokesh Kumar Bramhane.
The application for the patent was published on October 09, 2026, under issue no. 41/2026.
Abstract: The present invention relates to an exact multiplier circuit (100) for multiplying a first 16-bit binary operand (102) and a second 16-bit binary operand (104). The multiplier circuit (100) comprises a partial product generation unit (106) configured to generate a plurality of partial product rows (108) by performing a logical AND operation between the first operand (102) and each bit of the second operand (104), a partial product reduction unit (110) comprising a plurality of successive reduction stages (112, 120, 126), each stage comprising a plurality of multi-bit adders (114, 122, 128) configured to pairwise add two rows to generate a single row, thereby reducing the partial product rows (108) to two remaining rows (130), and a final adder (132) configured to add the two remaining rows (130) to generate a final product output (134) representing the exact product of the first operand (102) and the second operand (104). By employing multi-bit adders in place of conventional one-bit full adders and compressors, the invention reduces the number of partial product reduction stages, thereby reducing propagation delay, hardware area, and power consumption, while providing an exact, error-free product. The invention is suitable for implementation in FPGA and ASIC technologies for use in floating-point multiplication units and other arithmetic-intensive applications.
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