MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202641124641 A) filed by Vellore Institute Of Technology on October 15, 2026, for Counterfactual Error Gap Learning For Latency-Aware Routing In Distributed Ai Inference Systems.
Inventors include A Sivaranjani; and Sajal Varshney.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: ABSTRACT COUNTERFACTUAL ERROR GAP LEARNING FOR LATENCY-AWARE ROUTING IN DISTRIBUTED AI INFERENCE SYSTEMS A latency- aware routing system for distributed artificial intelligence inference includes a gateway router (100) between an edge inference node (114) and a cloud inference node (116), a request feature extractor (102) generating a feature vector from an inference request, a latency predictor (104) estimating an execution latency for each node, and a decision engine (108) selecting one node for execution based on the estimated execution latencies. A counterfactual estimator (110) estimates an execution latency of the node not selected without executing the inference request thereon. A counterfactual error gap learning learner (112) computes a factual prediction error and a counterfactual prediction error, computes a counterfactual error gap as a difference therebetween, weights the counterfactual error gap by an adaptive weighting factor derived from a rolling variance of recent prediction errors, and updates the latency predictor (104) with a learning signal derived therefrom. (Fig. 1)
Disclaimer: Curated by HT Syndication.
