MUMBAI, India, Aug. 17 -- Intellectual Property India has published a patent application (202641095863 A) filed by G. Pullaiah College Of Engineering And Technology on August 07, 2026, for Design And Implementation Of 18nm Finfet Based Comparator.
Inventors include Dr N. Geetha Rani; S. Fowzia Sultana; Boda Eramma; and T. Ranjitha Devi.
The application for the patent was published on August 14, 2026, under issue no. 33/2026.
Abstract: In analog-to-digital converters (ADCs), comparators are crucial components that convert analog input levels into digital decisions. However, when technology advances into deep-nanometer nodes, conventional CMOS-based comparators experience short-channel effects, leakage currents, variability, and decreased noise margins. The speed and power efficiency of contemporary high-resolution ADCs are diminished by these constraints. FinFET (Fin Field-Effect Transistor) technology has emerged as a highly promising alternative to planar CMOS because it offers improved electrostatic control over the channel, considerably decreased leakage current, and increased drive current capability. The design and implementation of an 18nm FinFET-based dynamic comparator using Cadence Virtuoso is presented in this study. The proposed comparator utilizes a dynamic latch architecture based on FinFET devices, which provides superior electrostatic control and dramatically reduced leakage compared to conventional 45nm planar CMOS implementations. The circuit operates in two well-defined phases: a reset (precharge) phase and an evaluation phase, both controlled by the clock signal. Cross-coupled latch transistors provide positive feedback that rapidly drives the output nodes to full logic levels, enabling very high- speed operation.
Disclaimer: Curated by HT Syndication.
