MUMBAI, India, June 22 -- Intellectual Property India has published a patent application (202641047831 A) filed by Hindusthan College Of Engineering And Technology on April 15, 2026, for Design And Physical Implementation Of Noc Router.
Inventors include Dr. N. J. R Muniraj; Dr. M. Ponmathy; B. Sharmila; S. Sathya; M. Prathiksha; and C. Parniga.
The application for the patent was published on June 12, 2026, under issue no. 24/2026.
Abstract: Abstract This article presents the RTL development and complete physical implementation of a parameterizable NoC router for scalable SoC applications. It has input- side VC FIFOs, XY routing logic, a separable switch allocator with a round-robin arbiter, and a low-latency crossbar with credit-based flow control for efficient and deadlock-free data transfer. It began with the development of the RTL code in Veri log HDL and then moved on to the synthesis phase using the Cadence Genus tool. After the RTL development and synthesis phase, the· physical implementation phase began with the use of the Cadence Innovus tool for floorplanning, placement, clock tree synthesis, and routing. After the completion of the routing phase, the timing analysis phase ensured the achievement of the timing requirements while minimizing the area and power of the chip. The complete design flow was implemented using Cadence tools as follows: • Simulation using NC-Launch • Synthesis using Genus • Physical design (placement, CTS, and routing) using lnnovus
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