MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202641127097 A) filed by Srm University-Ap on October 24, 2026, for Dual-K Spacer Structure For Multi-Channel Gate-All-Around Nanosheet Field-Effect Transistors And Method Therof.
Inventors include Piduguralla Kranthi; Annavarapu Ratnavali; and Dr. Patta Supraja.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: The present invention provides a multi-channel gate-all-around nanosheet field-effect transistor (100) comprises vertically stacked silicon nanosheets (110a, 110b, 110c) between a source region (104) and a drain region (106), a metal gate electrode (108) surrounding the nanosheets, and a segmented dual-k spacer (118) between the gate electrode (108) and the source and drain regions (104, 106). The spacer (118) comprises a low-k silicon dioxide segment (120) of 4 nm and a high-k hafnium dioxide segment (122) of 3 nm, giving a total engineered spacer length of 7 nm. The low-k segment (120) limits parasitic coupling and gate-to-source/drain capacitance, while the high-k segment (122) strengthens electrostatic control adjacent to the gated channel. The unequal allocation, selected for the highest switching ratio, suppresses OFF-state leakage and short-channel effects while preserving ON-state current and analog/RF performance. Figure of Abstract – Fig. 1
Disclaimer: Curated by HT Syndication.
