MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202527128041 A) filed by Inova Semiconductors Gmbh on December 17, 2025, for Efficiently Transmittable Bit Sequence With Restricted Disparity, And Encoded Forward Error Correction.
Inventors include Kluge, Fabian; and Neumann, Roland.
The application for the patent was published on October 02, 2026, under issue no. 40/2026.
Abstract: The present invention relates to a method for generating a bit sequence that can be transmitted efficiently and has a limited disparity and a limited run length. The proposed method allows data to be able to be transmitted particularly efficiently on a transmission channel. Compared to the prior art, the invention offers, among other things, the advantage that the physical behaviour on a transmission channel can always be deterministically controlled despite a reduction in resource requirements. Thus, according to the proposed method, bit errors are minimal and a transmission error can be corrected efficiently, i.e. with minimal technical effort. Furthermore, the encoders used are designed with a minimal number of gates, and the proposed method implicitly includes an form of nesting that allows so-called burst errors to be corrected particularly advantageously.
Disclaimer: Curated by HT Syndication.
