Intellectual Property India Publishes Patent Application for Flexible Cover-Lay Stencil Technique For Selective Filling Of Through –via Using Room Temperature Vulcanized Silicon Paste In Solder Finished High Density Pcbs For High Reliability Electronics Applications

MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202641094203 A) filed by Indian Space Research Organization on August 04, 2026, for Flexible Cover-Lay Stencil Technique For Selective Filling Of Through –via Using Room Temperature Vulcanized Silicon Paste In Solder Finished High Density Pcbs For High Reliability Electronics Applications.

Inventors include Amrendra Pratap Singh; Hanumanth Rao C.; Selvan C; Shivanandayya S. A.; Sujitha K. N; Shriram N Bhat; Selvi R; and James M P.

The application for the patent was published on August 07, 2026, under issue no. 32/2026.

Abstract: ABSTRACT OF THE INVENTION Flexible Cover-lay Stencil Technique for Selective Filling of Through –via using Room temperature vulcanized silicon paste in Solder Finished High Density PCBs for High Reliability Electronics Applications The proposed invention relates to flexible cover-lay stencil technique for selective filling of through –via using room temperature vulcanized silicon paste in solder finished high density PCBs for high reliability electronics applications. To avoid entrapment of flux residues and cleaning solvents, in the solder-finished multilayer PCB with flexible single side adhesive, Kapton coverlay stencil technique is developed using silicone-based room temperature vulcanizing (RTV) compound. In this technique, a suitable stencil is prepared by drilling the selective vias through CNC with Excellon drill file. The prepared stencil is then laminated under hot roll laminator with the solder mask coated and hot air solder levelled PCB. Selective open vias are filled with RTV using manual squeegee method and cured at room temperature. Filled vias are micro-sectioned initially and after the thermal cycling and thermo-vacuum tests to evaluate the quality and reliability of filling. The RTV silicone filled vias do not have any degradation in the bulk properties and are free from air pockets within the polymer matrix and readily complies with outgassing specifications.

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