MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202541000667 A) filed by Hiindusthan Institute Of Technology on January 03, 2025, for Fpga Implementation Of High Speed And Area Efficient Carry Skip Adder.
Inventors include Dr. C. Natarajan; S. Suganya; Dr. B. Paulchamy; Dr. A. Purushothaman; and K. Anantheeswar.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: 7. ABSTRACT OF THE INVENTION: Adder is one of the main building blocks in Digital Signal Processing (DSP) applications. There are different types of adders, each have their own advantages and disadvantages. The carry skip adder is efficient when compared to all other adders. Modified Carry Skip Adder (CSKA) has high speed and lower area when .compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA). structure. In addition, instead of utilizing multiplexer the proposed structure makes use of AND-OR (AOI) and OR-AND Invert (OAl) Compound gates for the skip logic. The structure is realized with both the fixed stage size and variable stage size which improves the speed and area of the adder. So the proposed structure is comparatively efficient in area and speed than the existing carry skip adder. This extension utilizes a modified parallel structure for increasing the speed and reducing the area. Xilinx software is usecl for the simulation process and this process is implemented in Cyclone-2 family FPGA development board .
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