MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202611070054 A) filed by Noida Institute Of Engineering And Technology Niet on June 04, 2026, for Hardware-Accelerated Spatiotemporal Feature Aggregation Apparatus For Real-Time Video Object Detection.
Inventors include Dr Mohammad Shahid; and Aarushi Thusu.
The application for the patent was published on August 07, 2026, under issue no. 32/2026.
Abstract: A hardware-accelerated spatiotemporal feature aggregation apparatus for real-time video object detection comprises an FPGA-based processing pipeline integrating a flow-guided temporal feature warping circuit (100), a scale-adaptive attention scoring circuit (200), a multi-scale feature pyramid accelerator circuit (300), and a region proposal and detection head circuit (400), governed by a deterministic pipeline state machine (500). A hardware-enforced isolation and attestation boundary (600) comprises an Input-Output Memory Management Unit (610) with write-locked page table registers, an interconnect firewall controller (620) with latched policy registers, an immutable configuration memory (630), and a monotonic counter attestation circuit (640). Upon completion of attention-weighted temporal aggregation, the pipeline state machine (500) asserts a commit signal triggering the IOMMU write-lock latch (614), firewall policy latch (624), and monotonic counter register (642), creating an atomic hardware state transition that secures feature data integrity, enforces bus access immutability, and extends the attestation chain for tamper-evident real-time video surveillance detection.
Disclaimer: Curated by HT Syndication.
