MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202641126822 A) filed by Vellore Institute Of Technology on October 24, 2026, for Hardware Sampling-Firewall Apparatus For Denying Steganographic Covert Channels In Language Model Output.
Inventors include Rajkumar S; and Aryan Hundia.
The application for the patent was published on October 30, 2026, under issue no. 44/2026.
Abstract: ABSTRACT HARDWARE SAMPLING-FIREWALL APPARATUS FOR DENYING STEGANOGRAPHIC COVERT CHANNELS IN LANGUAGE MODEL OUTPUT A hardware sampling-firewall apparatus interposed on an output data bus of a large-language-model inference accelerator downstream of upstream logit computation circuitry (000) includes a logit bus tap (101) receiving logit data, a probability distribution buffer (102) holding a per-token token-probability distribution, and a hardware true random number generator (200) generating physical, non-algorithmic randomness. A low-mass/near-tie candidate ranker (103) identifies a low- probability-mass region and near-equal-probability candidate tokens. A keyed perturbation seed register (203) holds a non-deterministic perturbation seed derived from the hardware true random number generator (200). A dither injector (301) injects seed-keyed dithering noise into the low-probability-mass region, and a tie-break randomizer (302) randomizes an ordering among the near-equal-probability candidate tokens. The logit bus tap (101), dither injector (301), and tie-break randomizer (302) form the sole physical signal path to token transmission, and a token output driver interlock (501) commits a sampled token after perturbation. (Fig. 1)
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