MUMBAI, India, June 22 -- Intellectual Property India has published a patent application (202641010549 A) filed by Vellore Institute Of Technology on February 01, 2026, for Method For Designing And Validating Stacked-Hexagonal Electric Double-Layer Supercapacitor Cells Using Multi-Scale Computational Simulations.
Inventors include Tejas Vijay; Jeff Joe Jacob; and Dr. Shankar Raman Dhanushkodi.
The application for the patent was published on June 12, 2026, under issue no. 24/2026.
Abstract: ABSTRACT: Title: Method for Designing and Validating Stacked-Hexagonal Electric Double-Layer Supercapacitor Cells Using Multi-Scale Computational Simulations The present disclosure proposes a method for designing and validating stacked-hexagonal electric double-layer supercapacitor (EDLC) cells (200) using multi-scale computational simulations integrating density functional theory (DFT), molecular dynamics (MD), and finite element method (FEM) to optimize electrode- electrolyte interfacial area, minimize internal resistance, and enhance specific capacitance, charge-discharge kinetics, cycle life, and structural durability. The stacked- hexagonal EDLC cell (200) comprises alternating layers of porous graphene-based electrodes (202), an electrolyte (204), ion-permeable separators (206), and metallic current collectors (208), arranged in a modular stacked-hexagonal cell geometry. a method that designs a compact stacked-hexagonal EDLC cell (200) featuring porous graphene-based electrodes to optimize electrode-electrolyte interfacial area while minimizing internal resistance, thereby enabling high specific capacitance, rapid charge-discharge rates, and extended cycle life.
Disclaimer: Curated by HT Syndication.
