MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202641087687 A) filed by B. M. S College Of Engineering on July 17, 2026, for Method For Power And Performance Efficient Binary Coded Decimal (bcd) Addition.
Inventors include Sathwik B C; Dr. Swetha P C; Dr. Srivinay; Mr. Girish K; Dr. Sneha S Bagalkot; and Dr. Amogh Pramod Kulkarni.
The application for the patent was published on July 24, 2026, under issue no. 30/2026.
Abstract: ABSTRACT Disclosed herein is a method (100) for power and performance efficient binary coded decimal (BCD) addition, the method (100) comprises receiving a first binary operand, a second binary operand, and an input carry signal, performing a carry look-ahead addition on the received operands and input carry signal to generate intermediate sum bits and an intermediate carry signal, directly generating corrected binary coded decimal output bits and a binary coded decimal carry output from the intermediate sum bits and the intermediate carry signal using combinational logic, computing the corrected binary coded decimal output bits and the binary coded decimal carry output in parallel without interdependency between individual output bit computations, producing a binary coded decimal (BCD) addition result comprising the corrected binary coded decimal output bits and the binary coded decimal carry output.
Disclaimer: Curated by HT Syndication.
