MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202641089818 A) filed by Dr. Mallepogu Sivalakshmi; Dr. Simhadri Mallikarjuna Rao; Dr. K. Anuradha; Chittibabulu Sape; K. John Paul; Sri Divya Gangiredla; Pukkalla Bharathi; and Suresh Sappa on July 23, 2026, for Multi-Layer Quantum Error Mitigation Architecture For Universal Quantum Computing.
Inventors include Dr. Mallepogu Sivalakshmi; Dr. Simhadri Mallikarjuna Rao; Dr. K. Anuradha; Chittibabulu Sape; K. John Paul; Sri Divya Gangiredla; Pukkalla Bharathi; and Suresh Sappa.
The application for the patent was published on July 31, 2026, under issue no. 31/2026.
Abstract: The present invention discloses a Multi-Layer Quantum Error Mitigation Architecture for Universal Quantum Computing configured to enhance the accuracy, reliability, and scalability of quantum computations through an intelligent, hierarchical error mitigation framework. The system continuously analyzes quantum hardware characteristics, predicts error propagation using artificial intelligence models, and dynamically applies the most appropriate mitigation strategies during quantum circuit execution. Unlike conventional approaches that rely predominantly on resource-intensive quantum error correction codes, the proposed architecture combines complementary mitigation techniques to significantly reduce computational errors while minimizing physical qubit overhead, execution latency, and resource utilization. The invention supports heterogeneous quantum computing platforms, including superconducting, trapped-ion, photonic, neutral atom, silicon spin, and hybrid quantum processors, ensuring broad compatibility and scalability. By enabling coordinated optimization across hardware, compiler, circuit, runtime, and measurement layers, the proposed architecture substantially improves quantum circuit fidelity, execution efficiency, and computational robustness.
Disclaimer: Curated by HT Syndication.
