MUMBAI, India, June 24 -- Intellectual Property India has published a patent application (202617061370 A) filed by Qualcomm Incorporated on May 14, 2026, for Multi-Stage Error Checking For Polar-Encoded Code Blocks.
Inventors include Horn, Idan Michael; Berger, Peer; and Landis, Shay.
The application for the patent was published on June 12, 2026, under issue no. 24/2026.
Abstract: Methods, systems, and devices for wireless communications are described. A network entity may insert one or more error check portions into a polar-encoded signal, where a first error check portion may protect a first portion of the polar-encoded signal. In some examples, a user equipment (UE) may determine a location for the first error check portion based on one or more decoding parameters and may transmit signaling requesting the determined location. The network entity may transmit the polar-encoded signal, and the UE may perform successive cancellation list (SCL) decoding of the polar-encoded signal, determining a first quantity of probable bit sequences for the first portion of the polar-encoded signal. The UE may reduce the SCL list size, make hard decisions on bit values for the first portion, terminate decoding early, or any combination thereof based on the first quantity of probable bit sequences and the first error check portion.
Disclaimer: Curated by HT Syndication.
