MUMBAI, India, June 22 -- Intellectual Property India has published a patent application (202641069334 A) filed by Easwari Engineering College on June 03, 2026, for Optimization Of Approximate Multiplier Circuit For Image Processing And Neural Network Applications.
Inventors include Dr. M. Priyadharshni; Vasu V S; and Varun J.
The application for the patent was published on June 12, 2026, under issue no. 24/2026.
Abstract: This work introduces an approximate design and implementation of an 8×8 multiplier system that aims at minimizing hardware usage, power dissipation, and latency without compromising the accuracy too much. In this respect, the emphasis is placed on the optimization of partial product reduction in order to achieve higher performance. This goal is accomplished by applying an approximation strategy in non-critical sections and retaining high-significance digits. The design has been developed using Verilog HDL code and has been successfully synthesized. Its error behavior has been analyzed via MATLAB simulation based on Error Distance, Mean Relative Error Distance, and Normalized Mean Error Distance parameters. The results demonstrate a substantial decrease in the number of hardware resources, as well as the improvement of area and power efficiency as compared to traditional multipliers. Considering the above properties, this architecture could be applied in numerous error-tolerant computing areas such as image and signal processing. Total Number of Words in Abstract: 149
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