MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202641090857 A) filed by Ram Sandeep Duvvada on July 27, 2026, for Performance Analysis Of Dynamic Comparators With/Without Tail-Controlled Transistor.
Inventors include Nagulakonda Kavya Meghana; Yamani Sudha Vani; Chatla Venkatalakshmi; Kiran Ramesh Rathod; Harika Pangam; Dama Durga Bhavani; Mulaparti Meena Kumari; and D. Ram Sandeep.
The application for the patent was published on July 31, 2026, under issue no. 31/2026.
Abstract: Dynamic comparators are widely used in high-speed and low-power mixed-signal circuits, particularly in analog-to-digital converters (ADCs), due to their fast operation and zero static power consumption. This work presents a performance analysis of dynamic comparators with and without tail-controlled transistors, namely the tail-less, single-tail, and double-tail dynamic comparator architectures. The comparators are designed and evaluated based on key performance parameters such as power consumption, propagation delay, and energy efficiency. The tail-less comparator offers a simple structure and fast operation but exhibits higher power consumption due to the absence of controlled current flow. The single-tail comparator improves power efficiency and reduces noise by incorporating a tail transistor. The double-tail comparator further enhances low-voltage operation, speed, and energy efficiency by separating the input and latch stages using two tail transistors. Simulation results demonstrate the advantages and limitations of each architecture, providing a comparative study that aids in selecting the most suitable dynamic comparator for low-power and high-speed VLSI applications.
Disclaimer: Curated by HT Syndication.
