MUMBAI, India, Aug. 17 -- Intellectual Property India has published a patent application (202617079901 A) filed by Telefonaktiebolaget Lm Ericsson Publ on June 29, 2026, for Programmable, Weighted, True Time Delay.
Inventors include Nilsson, Vejde; Snygg, Vilgot; Lindstrand, Jonas; and Akbar, Rehman.
The application for the patent was published on August 14, 2026, under issue no. 33/2026.
Abstract: A programmable, weighted, true time delay circuit is described The delay circuit comprises a plurality of weighted delay blocks (i.e., each having a different delay) connected in series, with a bypass path around each. An RF signal is delayed a desired amount by selectively utilizing some delay blocks by passing the RF signal through them, and bypassing the RF signal around the non-5 utilized delay blocks. In one aspect, the weighting is binary, and the control signals defining the delay comprise a digital word. When a delay block is not utilized, it exhibits high isolation so that all of the RF signal flows through the associated bypass path. The isolation is by high impedance and low-pass filtering; there are no series switches in the delay block. Conversely, when a delay block is utilized, its bypass path exhibits high isolation to prevent RF signal leakage around the delay block.
Disclaimer: Curated by HT Syndication.
