MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202641087372 A) filed by A Gulk Technology OPC Private Limited on July 16, 2026, for Prompt Based Chip Design Graphical Architectures To Rtl Generation.
Inventor includes Sriram Krishna Kakarla.
The application for the patent was published on July 31, 2026, under issue no. 31/2026.
Abstract: An Electronic Design Automation tool for an Architecture to Netlist which includes AI based methodology of an Integrated Circuit Design. A typical EDA based IC design starts from Verilog based/schematic design to netlist. Modern approach for small design is prompt based Verilog to netlist design. We are introducing novel approach of EDA tool where prompt-based architecture to netlist which improves efficiency of design process by eliminating the glitches which might occur during the non-EDA based interconnect architecture to netlist. In IC design like processors or large complex functionalities or reliable and robust chip design are requires four architectures of chip design such as Logic architecture, Design for Testability architecture, Power architecture, and Timing architecture. In Verilog/Schematic based design to netlist all these four architectures are design independently. Prompt based architecture eliminates redundant or legacy features which improves Power, Performance and Area. Architecture with prompt-based EDA approach brings interconnection for these four architecture editors starting from the project which improves turnaround time and improve the efficiency of the design. Design specific constraints can also be derived automatically based on the nature of the logic and design which also provides block level automated implementation design specific constraints. In addition, benefit of handling the design at multiple phases and at project to project.
Disclaimer: Curated by HT Syndication.
