MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641076796 A) filed by Vellore Institute Of Technology on June 21, 2026, for Segment-Selective Ternary Content Addressable Memory Architecture With Index-Based Activation.
Inventors include Aarthy M; and M. Kavipriya.
The application for the patent was published on July 03, 2026, under issue no. 27/2026.
Abstract: The present invention relates to a segment-selective ternary content addressable memory architecture (100). The architecture (100) comprises a memory array partitioned into a plurality of memory segments, an index interpretation module configured to derive an index value from input search data, a segment determination module configured to map the index value to a selected memory segment according to predefined grouping logic, and a control logic module configured to generate segment enable signals and row enable signals. The row enable signals activate only memory rows associated with the selected memory segment while remaining memory rows remain inactive. Comparison circuitry performs parallel comparison within the activated rows and generates matchline outputs that are processed by a priority encoder to generate a match output. The architecture employs distributed control logic for segment selection and enables deterministic activation of a selected memory segment during search operations.
Disclaimer: Curated by HT Syndication.
