MUMBAI, India, Aug. 10 -- Intellectual Property India has published a patent application (202647089311 A) filed by Qualcomm Incorporated on July 22, 2026, for Semiconductor Die Having A Die Interconnect And A Die Level Distribution Metallization Layer Including A Metal Line And A Metal Pad.
Inventors include Sun, Yangyang; Hu, Wei; He, Dongming; and Zhao, Lily.
The application for the patent was published on July 31, 2026, under issue no. 31/2026.
Abstract: A semiconductor die having a die interconnect and a die level distribution (DLD) metallization layer having a metal line and a metal pad having a width greater than the width of the metal line to support a larger die interconnect for improved signal path conductivity between the die interconnect and the metal pad is disclosed. Related integrated circuit (IC) packages and fabrication methods are also disclosed. The die includes a semiconductor layer, a DLD metallization structure, and a back end of line (BEOL) interconnect structure between the semiconductor layer and the DLD metallization structure. The DLD metallization structure mechanically supports die interconnects for coupling the die to another device, such as a package substrate or another die, and redistributes signals (e.g., power, ground, information) between the die interconnects and the semiconductor layer through the BEOL interconnect structure.
Disclaimer: Curated by HT Syndication.
