Intellectual Property India Publishes Patent Application for Single Hybrid System-On-Chip (soc) Die Structure With High Memory Bandwidth And Density

MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202647094324 A) filed by Qualcomm Incorporated on August 04, 2026, for Single Hybrid System-On-Chip (soc) Die Structure With High Memory Bandwidth And Density.

Inventors include Kang, Woo Tag; Wang, Zhongze; Badaroglu, Mustafa; and Chidambaram, Periannan.

The application for the patent was published on August 07, 2026, under issue no. 32/2026.

Abstract: A three-dimensional (3D) stacked chip package is described. The 3D stacked chip package includes a die having a wide input/output (IO) logic die area and a system- on-chip (SoC) logic die area isolated from the wide IO logic die area. The 3D stacked chip package also includes a memory stack on the wide IO logic area of the die. The 3D stacked chip package further includes a package substrate supporting the die.

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