MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202548125213 A) filed by Qualcomm Incorporated on December 11, 2025, for Small Loop Delay Clock And Data Recovery Block For High-Speed Next Generation C-Phy.
Inventors include Duan, Ying; Wu, Jing; and Chou, Shih-Wei.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: ABSTRACT SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C- PHY A clock recovery apparatus comprising: a pulse merger circuit having a plurality of inputs, a plurality of delay circuits, each of the plurality of delay circuits associated with a respective one of the plurality of inputs, a plurality of logic gates, each of the plurality of logic gates having a first input coupled to the respective one of the plurality of inputs and a respective one of the plurality of delay circuits, wherein each of the plurality of logic gates comprises an exclusive OR-gate, and a logic circuit having a plurality of inputs coupled to a plurality of outputs of the plurality of logic gates, and an output coupled to an output of the pulse merger circuit; and a clock recovery circuit having a sequential logic circuit and a delay circuit, wherein a clock input of the sequential logic circuit is coupled to the output of the pulse merger circuit, an output of the sequential logic circuit is coupled to an input of the delay circuit, and an output of the delay circuit is coupled to a reset input of the sequential logic circuit.
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